-Quad. D-type Flip-Flops with Clear
-Package: SOIC 16Pin (JEDEC)
-호환제품: HD74LS175RPEL, SN74LS175RPEL, DM74LS175RPEL...
:: General Description ::
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) versions feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.
:: Features ::
- LS175 contains four flip-flops with double-rail outputs
- Buffered clock and direct clear inputs
- Individual data input to each flip-flop
- Applications include:
- Typical clock frequency 40 MHz
- Typical power dissipation per flip-flop 14 mW
- Alternate Military/Aerospace device (54LS174, 54LS175) is available. Contact a National Semiconductor
Sales Office/Distributor for specifications.
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