- 품명: HD74LS148P
- 8-to-3-linePriority Encoder
:: Features ::
- Package: DIP 16Pin
- 메이커별 호환제품 Suffix:SN(TI), SN(On-Semi), HD(Hitachi), DM(Fairchild)
- The 74LS147 are Priority Encoders. They provide priority decoding of the
inputs to ensure that only the highest order data line is encoded.
Both devices have data inputs and outputs which are active at the low logic level.
The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied
decimal zero condition does not require an input condition because zero is
encoded when all nine data lines are at a high logic level.
The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By
providing cascading circuitry (Enable Input EI and Enable Output EO) octal
expansion is allowed without needing external circuitry.
The SN54/ 74LS748 is a proprietary Motorola part incorporating a built-in
deglitcher network which minimizes glitches on the GS output. The glitch
occurs on the negative going transition of the EI input when data inputs 0–7
are at logical ones.
The only dc parameter differences between the LS148 and the LS748 are
that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on
the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a
fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148.
The only ac difference is that tPHL from EI to EO is changed from 40 to 45 ns.